Currently, manufacture processes for advanced Complementary-Metal-Oxide-Semiconductor Field Effect Transistors (CMOS FETs) may be generally classified into two categories, i.e., Gate-First Process and Gate-Last Process.
The Gate-Last process is widely used in advanced integrated circuit manufacture. In this process, typically, a sacrificial gate and source/drain regions are formed and then the sacrificial gate is removed. A replacement gate stack comprising a high-K dielectric layer and a metal layer is then formed in a gate opening left due to removal of the sacrificial gate. As the gate is formed after the source/drain regions, it does not go through high-temperature annealing process, and thus materials for the gate can be more various and intrinsic characteristics of the materials can be exhibited more sufficiently.
With continuous scaling down of semiconductor devices, more critical requirements are proposed with respect to performances thereof. Stress Engineering has been employed to improve channel carrier mobility by introducing different stresses into respective channel regions of NMOS and PMOS devices, in order to enhance device performances. In the Gate-Last process, a metal material is typically filled in the opening left due to removal of the sacrificial gate to form a top metal gate electrode. It is desired to develop a filling method in formation of the replacement gate to further improve the channel carrier mobility for scaled-down devices.